Using a One-Hot State Assignment

Using a One-Hot State Assignment

As in PGAs, each logic cell contains two flip-flops, minimization of number of flip-flops is necessary for any design. So that the total number of logic cells used and the interconnections between the cells can be reduced. A one-hot state design can be used to design faster logic i.e., the number of cells required to realize each equation can be reduced.

It uses one flip-flop for each state => a state machine with N states requires N flip-flops. Eg.: a system with four states (T0,T1,T2 and T3) can use four flip-flops (Q0,Q1,Q2 and Q3) with the following state assignment:

T0: Q0Q1Q2Q3=1000, T1:0100, T2:0010, T3:0001

ð  The other 12 combinations are not used

ð  The next state and output equations can be written by inspection of the state graph or by tracing link paths on an SM chart.

Fig.1: Partial State Graph

Consider the partial state graph shown in fig.1, the next state equation for flip-flop Q3 can be written as

Q3⁺=X1Q0Q1’Q2’Q3’+X2Q0’Q1Q2’Q3’+X3Q0’Q1’Q2Q3’+X4Q0’Q1’Q2’Q3

Since Q0=1 => Q1=Q2=Q3=0 then the term Q1’Q2’Q3’ term is redundant and hence can be neglected. Then using similar case all the primed state variables can be eliminated from the other terms, then the next-state equation reduces to

Q3⁺=X1Q0+X2Q1+X3Q2+X4Q3

ð  Each term has exactly one state variable.

ð  Similarly each output equation contains exactly one state variable

Z1=X1Q0+X3Q2     Z2=X2Q1+X4Q3

When a one-hot assignment is used, the next-state equation for each flip-flop will contain one term for each arc (or link path) leading into the corresponding state. Hence in general, each term in every next-state equation and in every output equation will contain exactly one state variable. For asynchronous network additionally a “holding term” is required for each next state equation.

Method-1:

For one-hot assignment, resetting the system requires that one flip-flop be set to 1 instead of resetting all flip-flops to 0. If the flip-flops used do not have a preset input then we can replace Q0 with Q0’ throughout. Hence the changes in assignment will be

T0:Q0Q1Q2Q3=0000, T1:1100, T2:1010, T3:1001

And the modified equations are

Q3⁺=X1Q0’+X2Q1+X3Q2+X4Q3

Z1=X1Q0’+X3Q2

Z2=X2Q1+X4Q3

Method-2:

To solve the reset problem without modifying the on-hot assignment, add an extra term to the equation for the flip-flop, which should be 1 in the starting state.

Eg.: consider eq.1and fig.2 for the main dice game control

Fig.2: SM chart for serially linked state machine

The next state equation for Q0 is Q0⁺=Q0Dn_roll’+Q2 Reset+Q3 Reset

If the system is reset to state 0000 after power-up, then add the term Q0’Q1’Q2’Q3’ to the equation for Q0⁺. Which then changes after the first clock to 1000 (T0) which is the correct starting state. In general both assignment with a minimum number of state variables and a one-hot assignment have to be tried to see which one leads to a design with the smallest number of logic cells. Based on the requirement the choice has to be made i.e., for faster speed choose the faster design. When a one-hot assignment is used more next state equations are required but in general both next state and output equations will contain fewer variables, and hence requires fewer logic cells to realize the equation. Equations with fewer variables require a single cell but for six variables require cascading two cells, for 7 variables require three cascading cells. As more cells are cascaded, the propagation delay increases and the operation will be slow.