Verilog Behavioral modelling of Dice Game

module gametest(rb,reset,sum,clk,roll,win,lose);

output rb,reset;

output[12:2] sum;

inout clk;

input roll,win,lose;

wire[3:0] tstate,tnext;

wire trig1;

wire i;

mem [11:0]arr;

parameter sumarray={7,11,2,4,7,5,6,7,6,8,9,6};

always #20 clk=~clk;

always@(roll,win,lose,tstate)

begin

case(tstate)

1’d0: rb=1’b1;

         Reset=1’b0;

         if(i>=12)

begin

tnext=1’d3;

else if(roll= =1)

begin

sum=sumarray[i];

i=i+1’d1;

tnext=1’d1;

end

end

1’d1:  rb=1’b0;

          Tnext=1’d2;

1’d2:  tnext=1’d0;

          Trig1=~trig1;

          if((win|lose) = =1) reset=1’b1;

1’d3: null;

endcase;

end

always@(posedge clk)

begin

if(clk= =1)  tsate=tnext;

end

endmodule

module test_tester();

reg/wire rb1,reset1,clk1,roll1,win1,lose1;

reg/wire [12:2] sum1;

dicegame d1(rb1,reset1,clk1,sum1,roll1,win1,lose1);

gametest g1(rb1,reset1,sum1,clk1, roll1,win1,lose1);

endmodule

module test_tester_tb();

reg ;

wire ;

test_tester t1();

initial

begin

trig1=1’b0; sum1=1’d2; point=1’d2;

#580 trig1=1’b1;

#900 trig1=1’b0;

#1060 trig1=1’b1;

#1380 trig1=1’b0;

#1540 trig1=1’b1;

#1700 trig1=1’b0;

end

initial $monitor($time, “ trig1=5b, sum1=%d, win1=%b,lose1=%b,point=%d”, trig1,sum1,win1,lose1,point);

initial #2000 $finish;

endmodule

 module game(rb,reset,clk,win,lose);

input rb,reset,clk;

output win, lose;

wire roll1;

wire [12:2]sum1;

dicegame d1(rb,reset,clk,sum1,roll1,win,lose);

counter c1(clk,roll1,sum1);

endmodule

module dicegame_diceeq(sp,eq,d7,d711,d2312,da,db,dc,a,b,c,point);

input sp,eq,d7,d711,d2312,da,db,dc,a,b,c;

input [12:2]point;

reg sp,eq,d7,d711,d2312,da,db,dc,a,b,c;

reg [12:2]point;

always@(clk)

begin

if(posedge clk)

begin

a=da;

b=db;

c=dc;

if(sp= =1)

point=sum;

end

end

win=b&(~c);

lose=b&c;

roll=(~b)&(c&rb);

sp=(((~a)&(~b))&(c&(~rb)))&((~d711)&(~d2312));

if(sum=1’d7)

begin

d7=1’b1;

else

d7=1’d0;

end

if((sum= =11)|(sum= =7))

begin

d711=1’b1;

else

d711=1’b0;

end

if((sum= =2)|((sum= =3)|(sum=12)))

d2312=1’b1;

else

d2312=1’b0;

end

if(point= = sum)

begin

eq=1’b1;

else

eq=1’b0;

end

da=(((~a)&(~b)&c&(~rb)&(~d711)&(~d2312)|a&(~c)|a&rb|(a&(~d7)&(~eq));

db=~a&~b&c&~rb&d711|d2312|b&~reset|a&c&~rb&eq|d7;

dc=~b&rb|~a&~b&c&~d711&d2312|b&c&~reset|a&c&d7&~eq;

endmodule

module counter(clk,roll,sum);

input clk,roll;

output[12:2] sum;

wire [6:1]cnt1,cnt2;

parameter cnt1=1’d1;

parameter cnt2=1’d1;

always@(posedge clk)

begin

if (clk= =1)

begin

if(roll= =1)

begin

if(cntl1= =6)

begin

cnt1=1’d1;

else

cnt1=cnt1+1’d1;

end

if((cnt1= =6) & (cnt2= =6))

begin

cnt2=1’d1;

else

cnt2=cnt2+1’d1;

end

end

end

end

sum=cnt1+cnt2;

endmodule