Verilog Code for a Simple memory model

Module ram6116(io,cs_b,we_b,addr);

Inout [7:0] io;

Input cs_b,we_b;

Input [7:0] addr;

reg [7:0] ram1 [255:0];

always@(we_b,cs_b,addr)

begin

if(cs_b==1)

io=8’bz;

else

begin

if (posedge(we_b))

ram1[addr]=io;

endif

if(we_b==1)

io=ram1[addr];

else

io=8’bz;

endif

end

endif

end

endmodule